Binary
Intelligence
Every year, one more bit falls. We are building for the floor.
Invariant — July 2026 · London, UK · → to navigate · every cyan link opens the derivation
High performance ≠ High precision arithmetic.
The bit-width for full-precision parity falls every year; weights lead, activations trail by ~two years. Ternary weights match today, binary weights ~2027–28, full binary (W1A1) by 2028–30.
Anchored on MMLU: GPT-3's 175B scored ~44 in 2020; by 2023 a 7B (Mistral) beat it; by 2024–25, 3–4B models (Phi-3, Qwen-class) clear it by 25+ points — GPT-3-class capability compressed ~50–80× in five years. GPT-4-class (~86 MMLU) went from a rumored ~1.8T MoE in 2023 to 32–70B dense in about two years.
Measured rates: capability density ×2 ≈ every 3.3 months[1] · compute for fixed capability halves ≈ every 8 months[2]. Multiply by the main trend — bits per weight halving — and capability per byte doubles every few months: the fit boundary runs toward the chip from both directions.
Low-bit research is accelerating.
The research world has noticed — quietly. Quantisation titles are 4.6× on arXiv since 2019 and 6× at the top venues, accelerating every year. ICML alone: 5 → 38 since 2023.
Title search, CS-classified arXiv & 11 top venues (NeurIPS · ICML · ICLR · CVPR · ACL …), July 2026. UAI: five papers in seven years.
Faster and more throughput.
Our binary chip will enable far lower latency and more throughput than can be achieved in the current paradigm.
one user · batch = 1 · tok/s
fully batched · tok/s
Log scale — each gridline is 10× · binary (W1A1) design point · click to switch binary ⇄ ternary
What will the new chip designs look like?
The same job, drawn as silicon. Hover any part for its cost.
Amber = supply-chain chokepoints · dashed = parts our design doesn't have.
N4 · TENSOR CORES~$2,500 for the pair — the world's best multiply-accumulate arrays. The only part about intelligence.
N4P · XNOR FABRIC~$400 — multipliers deleted: sign-match gates, popcount trees, integer thresholds. The binary MACs are <20 mm² of this die.
NONE−$5,500 — deleted. The model is on-die; there is nothing to stream.
N4 · ~750 mm²~$350 — more FP compute than anyone can feed at batch 1.
70B NEVER WILLThe 32 GB ceiling: a 30B at 4-bit (15 GB) squeezes in — but every token still streams it through GDDR, and the 70B frontier is permanently out of reach.
N4P · XNOR FABRIC~$400 — same fabric as the datacenter part, binned for batch-1.
NONEDeleted. No VRAM to be too small — the model lives in the silicon.
AMPERE GPU · 8 nm~$70 — 67 INT8 TOPS that batch-1 decode can't use: it waits on memory.
1 GB MEMORY + XNOR FABRIC~$16 of silicon on a fully depreciated node (~$34 full BOM) — memory and logic on the same die. The whole 8B model loads once at boot.
TOKEN PATHDeleted. The decode ceiling moves from 102 GB/s shared LPDDR to on-die memory: ~20× the physics.
(ESP32-CLASS)~$2 — runs a menu, not a mind.
SOMEONE ELSE'S DATACENTERThe real bill. A subscription forever, 300–800 ms away, your kitchen audio in the cloud — and dead the moment the network drops.
3B MODEL + XNOR FABRIC~$7 of silicon — 3B binary = 375 MB on ~135 mm² of ancient, fully-depreciated CMOS. A $3,000 wafer yields ~440 of these.
Regions are stylised, costs are order-of-magnitude BOM estimates — full accounting one click deep. All numbers are the binary (W1A1) design point; ternary variants live in the appendix. Our prices are input costs at scale (BOM) — pricing and margin deliberately TBD; theirs are street prices. Edge shown is the value tier (mature 28 nm — always several times cheaper than a Jetson); the sub-watt N5 flagship ($399, 500 tok/s) fights Thor on the Edge duel slide. Datacenter spec → Edge spec → Cost model → Rack math → Future ladder → vs Cerebras → vs CPUs → Op energy → Token energy →
Instant deep research.
AlphaGo out-searched, not out-smarted, Lee Sedol. o1 rediscovered this trick for language. Capability is parameters × attempts[1][2]. The bottleneck is latency. A 250-attempt search takes ~18 min today; on our architecture, ~22 s.
World models
Planning is imagining futures faster than they happen. At 11,400 tok/s per stream, a world model rolls out thousands of candidate futures per second — model-predictive control becomes model-predictive reasoning.
Robotics
A 100 Hz control loop leaves 10 ms per decision. Their best stream fits ~2 tokens in that window. Ours fits ~114 — a full thought between steps, on-device, deterministic, no network.
Always-on intelligence
At ~10 mJ/token on $14 silicon, thinking becomes ambient: appliances, wearables and sensors running a continuous inner monologue — offline, private, on a nightlight's power. That's the Super-Edge chip, one slide back.
Solving AGI bottlenecks.
You can buy the GPUs. You can't plug them in. Grid interconnection queues run years. We draw 100× less.
The heat has nowhere to go without water. At 132 kW per rack, air physically cannot remove the heat: chiller plants, cooling towers, and ~1.9 litres evaporated per kWh. Water permits and local politics now decide where AI gets built. Our water bill rounds to zero.
The GPU is mostly a memory-delivery vehicle. HBM stacks and CoWoS are sold out on multi-year allocation. Our weights live in on-die SRAM on mature nodes — no HBM, no CoWoS, nothing on allocation. The queue doesn't exist for us.
Roadmap, staging & what each step costs
Two levers, one payoff — one corner.
Remove the multiply · fit the model on-die · and the cheapness that follows. The far corner (★) is best — every rival maxes one edge. Drag to rotate; click a point for detail.
Competing approaches — in detail.
Analog compute (Mythic, memristor crossbars, IBM PCM). Strengths: physics does the summation — extraordinary efficiency on paper. The wall: the weights drift, the devices vary, precision stalls at ~4–6 bits, and digitising every edge costs ~58% of the power. Great physics; unshippable determinism.
Pure digital logic. Strengths: the fastest inference physically possible — ~0.25 ns per layer, no memory fetch, no adder tree, zero standby state; unbeatable for compiled boolean rules. The wall: no continuous accumulation — it has never scaled to language.
In-memory compute (analog IMC; digital IMC like d-Matrix and IBM NorthPole). Strengths: kills the von-Neumann shuttle — compute moves to the data; the digital flavours are deterministic and actually shipping. The wall: analog flavours inherit the ADC tax and the noise; digital flavours give back most of the density win — and every flavour is still accelerating multiply-accumulate. Fixes the shuttle, keeps the multiply.
Digital binary near-memory — our lane. Bits stay bits: no ADCs, no DACs, no drift, logic-grade yield on mature CMOS with V-Cache-proven bonding. The multiply isn't accelerated — it's deleted, and the model lives next to the logic, so the memory wall dies in the same move. The only approach where both assassinations succeed — deterministically, on boring silicon.
DRIVERSRow drivers — every input needs digital→analog conversion before the array can use it.
CONDUCTANCE = WEIGHTThe physics is the pitch: summation for free by Kirchhoff's law. The physics is also the problem: conductance drifts with temperature and age, device variability corrupts weights, and precision tops out ~4–6 bits (Sebastian et al., Nat. Nanotech 2020).
LOOPSForever-calibration — compensating drift is a permanent tax, not a one-off.
BITSBinary inputs enter one side…
LAYER~12 ps per gate, ~0.25 ns per layer — no memory fetch, no adder tree; the signal ripples through combinationally.
LAYER~12 ps per gate, ~0.25 ns per layer — no memory fetch, no adder tree; the signal ripples through combinationally.
LAYER~12 ps per gate, ~0.25 ns per layer — no memory fetch, no adder tree; the signal ripples through combinationally.
LAYER~12 ps per gate, ~0.25 ns per layer — no memory fetch, no adder tree; the signal ripples through combinationally.
MAC-IN-BITCELLKills the shuttle, keeps the multiply. Compute moves into the array, but the operation being accelerated is still multiply-accumulate on multi-bit values.
d-MATRIX · NORTHPOLEThe digital escape: deterministic, shippable (IBM NorthPole, Science 2023; d-Matrix Corsair) — but bit-cells with logic sacrifice most of the density win.
MULTIPLYINGThe shared ceiling: every IMC flavour accelerates the old math. None deletes it.
INTEGER THRESHOLDSThe multiply is deleted, not accelerated: "do the signs match?" gates, popcount trees, 12-bit accumulators. Bits stay bits — deterministic by construction.
NO DACNothing to digitise — the array never leaves the digital domain.
The scoreboard that matters: the largest model each approach has ever demonstrated end to end. Three of the four lines have been flat for years — at toy scale.
Only one post-multiply approach has ever trained a language model end to end — and it's already at parity: BitNet b1.58, 2B params / 4T tokens[1] · TII ships ternary Falcon-E at 1B & 3B[2]. Analog CIM's flagship: a 45M-param inference demo[3]. Logic-gate networks: CIFAR-scale[4]. NorthPole runs a 3B model — trains nothing[5].
The Team.
Double first in physics and ML PhD, Oxford — spectral machine learning under Stephen Roberts. Huawei AI Theory & Amazon ML. NeurIPS / ICML / JMLR ×2.
Represented Uzbekistan at the International Mathematical Olympiad and the informatics olympiads · NUS data science · published with Diego.
Ten years as CTO of sureCore, leading its low-power SRAM and in-memory-compute IP. Technical Design Authority at Fractile. Tape-out experience to 6nm.
Already a technique.
We solve the mathematically intractable optimal brain damage problem.
Our novel method safeguards reasoning capacity in LLMs when going from 16-bit to 3-bit.
Team with traction.
Quantisation as a Service — live and selling. Send the checkpoint; we put precision where the model is fragile and ship in days.
Oscar Wang and Stephen Lin are closing engagements now and building partnerships in Taiwan.
16 → 3.8 bits, sold today → 1.58 → 1 in silicon.
One architecture. Four markets.
The same binary near-memory fabric — the multiply deleted, the model resident on-die, no HBM — scaled by die size and process node from a datacenter package down to a $14 chip.
Silicon TAM — chip content only, never end-market revenue. Datacenter figure is batched peak; the rest are single-stream. Input costs are order-of-magnitude BOM at scale. Binary (W1A1) design point. Full floorplans, part by part →
The future is
binary
The floor is published. The bet is ours. — investment@invariant.fyi
Energy per operation
| Operation | Published silicon | ~4–5 nm estimate | vs binary |
|---|---|---|---|
| FP32 multiply-accumulate | 4.6 pJ @45nm | ~1.5 pJ | ~500× |
| FP16 multiply-accumulate | ~1.5 pJ @45nm | ~0.5 pJ | ~170× |
| INT8 multiply-accumulate | 0.2 pJ @45nm | ~0.07 pJ | ~25× |
| Ternary op (sign-gated INT8 add) | — | ~12 fJ | ~4× |
| Binary XNOR + popcount | 21.6 fJ @22nm — silicon-proven | ~3 fJ | 1× |
| 8 KB SRAM access (word) | 10 pJ @45nm | ~2 pJ | — |
| Off-chip DRAM access (word) | 1–2 nJ | HBM ~6 pJ/bit | — |
The op gets so cheap that the budget moves to wires and memory — which the memory-wall math then guts.
Assumptions
- 21.6 fJ/op @22nm is measured, synthesizable digital silicon (XNOR Neural Engine) — not a projection
- 22nm → 4–5nm scaling of ~5–7× (V² + capacitance across ~4 nodes)
- 3 fJ covers XNOR + count + operand latch; weight SRAM reads are a separate budget line — no double counting
- ternary op = zero-gated add of an INT8 activation, ~12 fJ incl. control
- 45nm figures: canonical Horowitz ISSCC 2014
Power, water, memory — in detail
| GPU today | Invariant-1 | Ratio | |
|---|---|---|---|
| Where weights live | off-package HBM3e | on-package SRAM | — |
| Energy per bit moved | ~6 pJ | ~0.2 pJ | 30× |
| Bits per weight | 8–16 (FP8/FP16) | 1 (1.6 ternary) | 8–16× |
| Energy per weight touched | ~48–96 pJ | ~0.2 pJ | 240–480× |
| 70B model footprint | 70–140 GB — needs HBM | 8.75 GB binary / 14 GB ternary — fits in SRAM | 10–16× |
Assumptions
- HBM ~6 pJ/bit (≈200 pJ per 32-bit word incl. PHY + controller)
- stacked-SRAM read ~0.2 pJ/bit incl. array + hybrid-bond vertical hop
- batch amortisation applies equally to both sides — ratios are batch-invariant
- 70B dense reference model throughout
| Today (100 MW AI site) | Invariant (1.5 MW) | |
|---|---|---|
| Rack density | 132 kW — air cooling physically impossible; 100% direct liquid, no fans in the rack | 18 kW — ordinary air-cooled racks |
| Plant | chillers, CDUs, cooling towers, 25–45°C facility water loops | dry coolers — no chillers, no towers, no facility water |
| Cooling energy share | 7–40% of facility power (PUE 1.1–1.54) | ~13% of a number 65× smaller |
| Water | WUE ~1.9 L/kWh → 4.56M L/day (range 2–5M by WUE) | ≈0 L/day |
| Heat rejected | ~100 MW thermal — a small power station | ~1.5 MW — an office building's HVAC |
Assumptions
- WUE 1.9 L/kWh industry average, evaporative; literature spans 1.0–2.5 — range shown
- chip packages may use closed-loop cold plates — the claim is no facility water and no chillers, not "no liquid anywhere"
- GB300 cooling requirements per NVIDIA/vendor deployment guides
| Today — 100 MW GB300 site | $ |
|---|---|
| Facility: AI fit-out $20–25M/MW (liquid cooling, high-density power) | $2.0–2.5B |
| Hardware: 606 racks × ~$3.5M | $2.1B |
| Total | ~$4.5B |
| Invariant — same 667M tok/s | $ |
|---|---|
| Facility: ~2 MW ordinary shell at $10.7M/MW | ~$21M |
| Hardware: 635 chips × $12k | $7.6M |
| Hosts, network, dry coolers | ~$5M |
| Total (>100× less; we state ">50×" on the main slide) | ~$34M |
Assumptions
- facility $/MW: 2025 construction cost indices; AI fit-out premium applied to the incumbent side only where justified
- $12k chip = ~2× BOM (BOM breakdown)
- ternary mode: 1,026 × $16k = $16.4M hardware → ~$45M total — still >100×
Energy per token — both sides, line by line
GB300 NVL72: 132,000 W ÷ 1,100,000 tok/s = 0.120 J/token (IT power)
× PUE 1.25 = 0.150 J/token at the meter
// check 1: prior gen GB200 = 120 kW ÷ 865k = 0.139 J — Blackwell Ultra improved 16% ✓
// check 2: H100 measured 0.39 J/tok — consistent generational curve ✓
// check 3: deployed frontier serving ≈0.31 Wh/query ≈ 2.2 J/tok — 18× worse than the floor we grant them
| Invariant-1 power budget | Binary @ 1.05M tok/s | W | Ternary @ 650k tok/s | W |
|---|---|---|---|---|
| MAC fabric | 1.47×10¹⁷ op/s × 3 fJ | 441 | 9.1×10¹⁶ op/s × 12 fJ | 1,092 |
| Weight SRAM reads | 95.7 TB/s × 8 × 0.2 pJ | 153 | 94.8 TB/s × 8 × 0.2 pJ | 152 |
| KV-cache reads (MLA + 4-bit) | 1.05M × 32.8 MB | 55 | 650k × 32.8 MB | 34 |
| INT8 vector unit (~1% of ops) | softmax/norm/rotary | 118 | same | 100 |
| NoC, partial sums, control | allowance | 200 | allowance | 200 |
| Leakage (power-gated) + IO | 6 dies | 100 | 9 dies | 130 |
| Total | ≈1.07 kW → 1.02 mJ/tok | 118× | ≈1.7 kW → 2.6 mJ/tok | 46× |
Assumptions
- 1.1M tok/s is offline + unverified MLPerf v5.1 (Azure, observed by Signal65) — the incumbent's best foot, granted
- rack at 132 kW — the bottom of Supermicro's 132–140 kW operating range: again favours them
- binary op 3 fJ, ternary op 12 fJ, stacked-SRAM 0.2 pJ/bit (op-energy table)
- decode batch 96, avg context 2,048, MLA + 4-bit KV
- softmax/norm/residual INT8 — standard in BitNet-class models
- Invariant-1 is specified, not taped out
Invariant-1 — diagram, nodes, cost, maturity
tok/s = batch × bandwidth ÷ weight-bytes
// their rack: 72 × 8 TB/s ÷ 35 GB (FP4) × batch/eff ≈ 1.10M ✓
// our chip (binary): 96 × 100 TB/s ÷ 8.75 GB = 1.097M → spec 1.05M tok/s
// our chip (ternary, trit-packed 1.6 b/w): 96 × 100 ÷ 14 GB = 686k → spec 650k tok/s
| Cost breakdown (volume BOM) | Binary (6 dies) | Ternary (9 dies) |
|---|---|---|
| SRAM dies, N5 HD (~$300 ea; redundancy-repairable → high yield) | $1,800 | $2,700 |
| Compute die, N4P (~500 mm², mature yields) | ~$400 | ~$400 |
| Hybrid bonding + package + test | $1,500–2,500 | $2,000–3,000 |
| Board, power delivery, LPDDR | ~$1,000 | ~$1,100 |
| BOM → sell price (≈2× BOM) | ~$5.5k → $12k | ~$7k → $16k |
| Technology | Who ships it today | Our exposure |
|---|---|---|
| Hybrid bonding, ~9 µm pitch | AMD 3D V-Cache — in production since 2022 (TSMC SoIC) | none — buying a mature flow |
| N5 high-density SRAM (0.021 µm²/cell) | every N5 product since 2020; SRAM stopped scaling at N3 — the cheap node IS the optimal node | none |
| N4P logic | mainstream mobile/DC silicon | none |
| XNOR-popcount fabric | silicon-proven at 22nm (XNE); trivially synthesizable | low — ours is bigger, not different |
| MLA + 4-bit KV | DeepSeek — shipping in production models | low — adopt, don't invent |
| W1A1 models at parity | nobody — this is the bet, and the moat | the company — this is the bet |
Memory budget
- binary: 8.75 GB weights + 3.1 GB KV (batch 96 × 2k ctx × ~16 KB MLA-latent 4-bit) + 0.15 workspace = 12 GB / 6 dies
- ternary: 14 GB weights (trit-packed, 1.6 b/w — BitNet.cpp's 5-trits-per-byte, shipping) + KV → 18 GB / 9 dies
- raw GQA-70B KV is 82 KB/tok at 4-bit → MLA ≈4–5× compression is an explicit, cited assumption
- long context pages to LPDDR at a disclosed ~2× derate at 32k — we never claim "all-SRAM" past ~4k average
- >70B and MoE: multi-package scale-out — only 1–2-bit activations cross packages, so the fabric is cheap wires; 2-die 2.5D stitch is the proven pattern, and MoE's params-per-FLOP favours on-die capacity (experts partition one-per-die)
- stack yield: assembled from known-good dies; SRAM redundancy repairs post-bond — the V-Cache flow, in consumer production since 2022
Thermal & risk, stated
- ~1.1 kW package: compute die sits beside the stack, not under it — logic heat never crosses 6 SRAM layers
- SRAM dies dissipate ~mW/mm² — stacking memory is thermally boring; stacking logic is not, and we don't
- closed-loop cold plate is the fallback; the claim is no facility water, no chillers
- Invariant-1 is specified, not taped out — printed on every chip slide on purpose
One chip vs one GB300 NVL72
| GB300 NVL72 | Invariant-1 (binary) | Ratio | Invariant-1T (ternary) | |
|---|---|---|---|---|
| Throughput (70B decode) | 1,100,000 tok/s | 1,050,000 tok/s | 0.95× | 650,000 tok/s |
| Power | 132,000 W | ~1,070 W | 123× | ~1,700 W |
| Energy per token | 120 mJ | 1.02 mJ | 118× | 2.6 mJ (46×) |
| Cooling | 100% liquid + facility water | air / closed loop | — | same |
| Memory | 20.7 TB HBM3e off-package | 12 GB SRAM on-package | — | 18 GB SRAM |
| Mass | ~1,360 kg | ~2 kg | ~700× | ~2 kg |
| Price | ~$3,500,000 | ~$12,000 | ~290× | ~$16,000 |
1.1M ÷ 72 = 15,278 tok/s per B300 at 1,833 W of rack share = 0.120 J/tok — same answer ✓
// ternary framing: one 1.7 kW ternary chip ≈ 42 B300 GPUs' worth of decode — on published science alone.
Assumptions
- 1.1M tok/s: Llama-2-70B, offline, unverified MLPerf v5.1 (Azure ND GB300 v6, FP4, TensorRT-LLM) — their best possible number, granted in full
- 132 kW = bottom of the published operating range (132–140)
- decode-dominated serving; prefill-heavy mixes narrow the gap — covered by the 3× derate in the cost model
- Invariant-1: specified, not taped out
Single-stream latency — the physics of interactivity
B300, granted FP4 (its best case): 35 GB ÷ 8 TB/s = 4.375 ms → 229 tok/s
B300 at FP8: 70 GB ÷ 8 TB/s = 8.75 ms → 114 tok/s
Invariant-1 binary: 8.75 GB ÷ 100 TB/s = 87.5 µs → 11,400 tok/s (+1.1 µs compute)
Invariant-1 ternary: 14 GB ÷ 100 TB/s = 140 µs → 7,100 tok/s
// binary = 50× their best case · ternary = 31× — on published science
| 100 TB/s — three independent feasibility legs |
|---|
| 1 · Throughput mode already sustains 95.7 TB/s (batch 96 × 8.75 GB × 10,937 steps/s) — no new assumption |
| 2 · Areal: 100 TB/s ÷ 4,800 mm² = 21 GB/s/mm² — AMD ships V-Cache at ~55–70 GB/s/mm². We need less than half of shipped. |
| 3 · AMD MI300X: 17 TB/s from one 256 MB layer, in production since 2023. We tile 6 far larger dies. |
Groq / Cerebras — the obvious objection, answered
- they proved SRAM inference wins latency — at FP8/16
- 70B at those widths needs ~576 Groq chips or a ~23 kW wafer
- binary is 16× denser: the same idea collapses into one 1 kW package — they validated the market; compression changes the answer
Assumptions
- weights re-read once per token at batch 1 — true of all decode
- 100 TB/s sustained / 120 peak across 6 bonded dies
- B300 batch-1 figures are theoretical BW ceilings — real GPUs land below them
Sources
AMD V-Cache 2+ TB/s MI300X 17 TB/s B300 8 TB/s HBM3e Cerebras, chip-to-chip → CPUs & bitnet.cpp →The 100 MW walk — iso-throughput
100 MW ÷ PUE 1.25 = 80 MW IT ÷ 132 kW/rack = 606 racks × 1.1M = 667M tok/s
// the same tokens on Invariant-1 (binary)
667M ÷ 1.05M = 635 chips × 1.15 kW (chip + fan share) = 0.73 MW
+ 28% hosts & network = 0.93 MW IT × PUE 1.15 (air) = ~1.1 MW best estimate
// conservative: chips at 850k, +40% overhead, PUE 1.2 → 1.5 MW — the headline survives the miss case
// ternary (published science): 667M ÷ 650k = 1,026 chips × 1.8 kW → ≈2.7 MW total = 37×
| Today | Binary | Ternary | |
|---|---|---|---|
| Racks | 606 × 132 kW, liquid | 40 × 18 kW, air | 64 × 18 kW, air |
| Facility power | 100 MW | 1.1–1.5 MW | ~2.7 MW |
| Grid interconnect | years in the queue | a commercial feeder | same |
Assumptions
- PUE 1.25 today (liquid AI build; the industry average 1.54 would flatter us — we don't use it)
- PUE 1.15 air replacement; 18 kW racks are catalogue equipment
- hosts/network +28% best / +40% conservative
- iso-throughput, 70B-class decode-dominated serving
Cost per token — both floors, line by line
$3,500,000 ÷ 35,040 h = $99.87/h
+ power: 132 kW × PUE 1.25 × $0.08/kWh = $13.20/h
= $113.07/h ÷ 3,960M tok/h = $0.029 / M tokens
// Invariant-1 floor, binary (same accounting)
$12,000 ÷ 35,040 h = $0.342/h + power $0.101/h + host share $0.06/h
= $0.503/h ÷ 3,780M tok/h = $0.000133 / M
× 3 derate (prefill share, <100% util, batch dilution) = $0.0004 / M → 72×
// per billion tokens (the main-slide unit): $29 them · 40¢ binary · 85¢ ternary
// ternary: $16k, 1.7 kW, 650k tok/s → $0.66/h ÷ 2,340M = $0.00028 ×3 = $0.00085 / M → 34×
70B-class output tokens sell for $0.60–0.90 / M today. Against our binary floor that is a 1,500–2,200× markup — labeled context, never our headline ratio. First mover on this floor sets the price and still runs 99% gross margin.
Assumptions — every derate lands on our side
- electricity $0.08/kWh industrial, both sides
- 4-year amortisation, no financing, both sides
- 3× serving derate applied only to us; their floor stays theoretical-perfect
- their rack priced at $3.5M (est. range $3–4M)
- BOM detail in chip spec
Invariant-E vs Jetson — batch 1, nothing hidden
| Device | 8B decode | Power | Price | tok/J | tok/s/$k |
|---|---|---|---|---|---|
| Jetson AGX Orin 64GB — 204.8 GB/s LPDDR5 | ≤51 ceiling · ~40 real | 15–60 W | $1,999 | ~0.9 | 20 |
| Jetson AGX Thor — 273 GB/s LPDDR5X, 2,070 TFLOPS FP4 | ≤68 ceiling · ~55 real | 40–130 W | $3,499 | ~0.6 | 16 |
| Invariant-E — 1 GB W1A1 on-die SRAM, 2 TB/s | 500 spec · 2,000 ceiling | 3 W | ~$399 | ~167 | 1,250 |
| Invariant-E ternary variant — 1.6 GB trit-packed | 250 spec · 1,250 ceiling | ~2.5 W | ~$449 | ~100 | 557 |
| Invariant-E Value — one monolithic 28 nm die, 1 GB on-die | 250 spec · ~750 ceiling | ~3 W | ~$69 | ~83 | 3,600 |
Jetson: LPDDR bandwidth ÷ 4 GB of FP4 weights. 2,070 TFLOPS of compute cannot help batch-1 decode.
Invariant-E: 2 TB/s on-die ÷ 1.0 GB = 2,000 tok/s ceiling — we spec 500 and spend the slack on power.
| Invariant-E energy per token (batch 1) | mJ |
|---|---|
| Weights: 8×10⁹ bits × 0.3 pJ/bit (mobile stacked SRAM) | 2.4 |
| XNOR compute: 16 Gop × 10 fJ | 0.16 |
| KV (windowed + MLA, LPDDR) | ~2 |
| SoC overhead, DRAM standby | 1–2 |
| Total → 6–9 mJ/tok → 100 tok/s @ 0.9 W · 500 tok/s @ ~3 W | 6–9 |
Assumptions
- Jetson "real" figures: public Jetson AI Lab / developer benchmarks for 7–8B at 4-bit; ceilings are bandwidth ÷ bytes — generous to Jetson (no efficiency loss assumed)
- Invariant-E: 1 GB SRAM die (~400 mm² N5-class, or 2×200 mm²), 0.3 pJ/bit; specified, not taped out
- KV windowed to 1–2k recent tokens + MLA — assistant workloads
- value tier = the 28 nm monolithic port: memory + logic on one fully-depreciated die, ~$34 BOM → ~$69 — always under a Jetson by a wide margin; the N5 flagship exists for sub-watt phone sockets
- the same architecture ports to 22–28 nm mature nodes for cost-down and sovereign supply (see roadmap)
Why this market is unwinnable for them
- their silicon must stream weights over LPDDR — the decode ceiling is physics, not engineering
- a 16× smaller model is the only way through, and it requires binary-native models they don't have
- always-on frontier AI at <1 W: phones, wearables, vehicles, robots, defence — the entire ambient-AI category is ours by default
Iso-power: what 100 MW buys under binary
Today: 100 MW → 667M tok/s (606 racks × 1.1M — see power walk)
Binary: (100 ÷ 1.5) × 667M = 44.5B tok/s (57B on the 1.1 MW best estimate — stated once, used never)
Ternary: (100 ÷ 2.7) × 667M = 24.7B tok/s
44.5×10⁹ × 86,400 = 3.8 quadrillion tokens/day ÷ 8.1×10⁹ humans ≈ 5.5 tok/s per human, continuously
Assumptions
- conservative 1.5 MW replacement basis (65×)
- 70B-class decode-dominated serving mix throughout
- world population 8.1B
Who buys it — and why they can't not
| Buyer | Why they move |
|---|---|
| Hyperscalers / frontier labs | power-constrained on every continent; every MW we free is a MW for training. A 72× token-cost floor is not a procurement decision — it's a board-level emergency for whoever moves second. |
| Neoclouds & API resellers | their entire P&L is $/token margin. First mover resets the market price and prints margin while GPU fleets serve at a loss. |
| Sovereign AI programs | a national inference grid for $35M and 1.5 MW — no US-scale grid, no exotic supply chain, sited domestically, running open or domestic models. |
| Enterprises (on-prem) | one 18 kW rack in an ordinary server room replaces the cloud contract; data never leaves the building. Compliance departments buy this before engineers do. |
Context
- AI datacenter power demand is the industry's stated #1 constraint (IEA; utility interconnect queues run years)
- inference, not training, is where token volume and power spend compound
- Invariant sells chips/systems or capacity on owned fleets — both priced against a 72× floor advantage
The evidence — and its limits, stated
| Result | What it showed |
|---|---|
| Snell et al. 2024 arXiv 2408.03314 | compute-optimal test-time scaling lets a smaller model beat one 14× larger, FLOPs-matched (MATH); adaptive allocation is 4× more efficient than best-of-N |
| Large Language Monkeys arXiv 2407.21787 | coverage scales log-linearly over 4 orders of magnitude of samples; DeepSeek-V2-Coder: 15.9% → 56% on SWE-bench Lite at 250 samples vs 43% frontier single-attempt SOTA |
| The reasoning era o1/o3, R1 | frontier gains now come from spending more tokens at inference — the industry already concedes that tokens are intelligence |
250 attempts × $0.0004/M ≈ the cost of 3.4 attempts at NVIDIA's own floor — or 0.1 attempts at API prices.
Token price is the exchange rate between money and intelligence. We moved it 72×.
Without automatic verifiers, sample-selection (voting, reward models) plateaus beyond a few hundred samples (Monkeys, limitations). Search pays best where answers can be checked — code, math, tools, agents — which is exactly where token volume is exploding.
Why this compounds with binary
- parity-per-token is the deck's premise; parity-per-dollar doesn't even need it — a weaker model with 72× the search budget already competes
- at 11,400 tok/s single-stream, a 10k-token reasoning chain completes in <1 s — search becomes interactive
- our cost floor converts directly into capability headroom no GPU fleet can match at iso-cost
Weight quantisation — timeline & method
| Date | Method | Bits/weight at ~parity |
|---|---|---|
| 2021 | FP16 deployed baseline | 16 |
| Aug 2022 | LLM.int8() | 8 |
| Oct 2022 – Jun 2023 | GPTQ · AWQ | 4 |
| Feb 2024 | QuIP# · AQLM — first Pareto-optimal <2-bit | 2 |
| Apr 2025 | BitNet b1.58 2B4T — native ternary, 4T tokens, matches FP16 peers. Open weights. | 1.58 |
| 2025 | ParetoQ (Meta) — sub-4-bit QAT scaling laws keep improving | 1.58–2 |
Extrapolation method — two axes, printed, falsifiable
- Axis 1 — bit-width: parity bit-width has halved every ~12 months for 4 consecutive years (log₂ falls ~1/yr)
- Axis 2 — scale: the size at which each low-bit result reaches parity climbs ~10× params per 1–2 yrs
- 70B is 1.5 orders above 2B → ternary parity at 70B-class ≈ 2027 (±1 yr)
- trend extrapolation, not a theorem — a bet stated at full strength, not a guarantee
Sources — every point on the chart
LLM.int8() GPTQ AWQ QuIP# AQLM BitNet b1.58 BitNet 2B4T weights ParetoQActivation quantisation — the harder axis
| Date | Method | Bits/activation |
|---|---|---|
| 2021 | FP16 baseline | 16 |
| Nov 2022 | SmoothQuant — W8A8 by migrating outlier scale into weights | 8 |
| Apr 2024 | QuaRot — rotate the network; outliers vanish; W4A4KV4 | 4 |
| 2024 | SpinQuant — learned rotations, ~2.9 pts from FP at W4A4KV4 | 4 |
| Nov 2024 | BitNet a4.8 — 4-bit activations on 1.58-bit weights, no loss vs b1.58 | 4 |
| proj. 2026 | A2 on ternary weights (rotations + native training) | 2 |
| proj. 2027–28 | A1 small-scale → W1A1 | 1 |
Add the scale lag (~1–2 yrs per 10× params) → W1A1 at 70B-class lands 2028–2030, median 2029. The lab's job is to land it early — and the ternary mode of this deck pays the bills while we do.
Assumptions
- same two-axis method as the weight timeline
- original BitNet (2023) used A8 — activations lag weights ~2 yrs consistently; the projection preserves that lag
- softmax/norm stay INT8 even at W1A1 (~1% of ops — budgeted in the power table)
Why the loop must close in one lab
| Player | Why they don't build this |
|---|---|
| GPU vendors | binary-in-SRAM deletes the HBM bill of materials they monetise. You do not disrupt your own margin structure; you get disrupted out of it. |
| Frontier model labs | no silicon teams; GPU-portable roadmaps by design. BitNet is Microsoft Research — shipped as a paper, because shipping it as a product requires a chip. |
| Chip startups | can't train models. A binary chip without binary-native weights is an empty socket. (See Groq: superb silicon, borrowed models, brutal economics.) |
| Hyperscaler TPU teams | fleet homogeneity rules; a W1A1 bet breaks their fleet years before it pays. |
| Milestones — each de-risks the next |
|---|
| 1 · 8B W1A1 at parity — our own run; the scientific result that prices everything |
| 2 · FPGA prototype — the decode law measured, not modelled |
| 3 · Invariant-1 tape-out — the spec in this deck, on mature nodes, no exotic supply |
Provenance
- our precision compiler already beats heuristic SOTA (GPTQ/AWQ-class) at 3- and 2-bit on coding benchmarks
- the same mathematics — loss-landscape curvature, not per-layer heuristics — is what goes below 2 bits
The honest risk
- NVIDIA can add binary tensor cores. What they cannot do quickly: abandon HBM economics, retrain frontier models binary-native, and clean-sheet the architecture. That cycle is measured in years — that's the window, and the moat is the loop, not the gate.
Team
Diego Granziol
FOUNDER & LEAD SCIENTIST
Oxford MPhys, double first; ML PhD at Oxford’s MLRG under Stephen Roberts — spectral machine learning. Huawei AI Theory & Amazon ML — deployed under real product constraints, including on-device. Two JMLR papers on the geometry of training (batch-size scaling via random matrix theory, 2022; iterate averaging, 2024) the RMT × deep-learning line with Keating & Baskerville, and the Safety–Efficacy Trade-off (ICML 2026, with Ulug’bek Abdimanobov).
Khurshid Juraev
CO-FOUNDER & LEAD ENGINEER
Represented Uzbekistan at the International Mathematical Olympiad; informatics olympiad. National University of Singapore, data science. Co-author, Hessian Spectral Analysis at Foundation Model Scale (2026, with Diego). Algorithms & systems — and the olympiad bench: nine engineers he trained or recruited, on call.
Jon Keating
FOUNDING ADVISOR
Fellow of the Royal Society; Fröhlich Prize. Quantum chaos and random matrix theory × the Riemann zeta function. Wills Professor at Bristol, then Sedleian Professor of Natural Philosophy at Oxford; President of the LMS; chaired the Heilbronn Institute (the GCHQ partnership) to 2020. Random matrices & spectral problems: the foundations of our compiler.
Tony Stansfield
FOUNDING ENGINEER
CTO of sureCore for a decade, leading design of the company’s low-power SRAM and in-memory-compute IP. Technical Design Authority at Fractile, the Gelsinger-backed in-memory-compute inference accelerator startup. Transistor-level and custom circuit design; tape-out experience across process nodes down to 6nm.
The mathematics that beats heuristics at 3 bits is the mathematics that gets to 1. This team wrote it.
What we sell, in what order
| Stage | Product | Economics |
|---|---|---|
| 0 · Now | Precision-compiler optimisation on customers' existing GPU fleets — the compiler that beats GPTQ/AWQ-class at 3-/2-bit ships as a service today | priced as a share of measured savings — revenue and design-win relationships before any silicon exists |
| 1 · Edge first | Invariant-E + SDK — OEM design wins in phones, vehicles, robotics, defence | value tier ~$69 (28 nm monolithic) to flagship $399–449 (N5, sub-watt) — both ≈2× BOM, vs $249–3,499 incumbents |
| 2 · Datacenter | Invariant-1 systems or capacity — sell 18 kW racks, or sell tokens per megawatt | capacity priced under market ($0.60–0.90/M) and >30× above our floor — ~99% gross margin on capacity at market price |
| 3 · Sovereign | Design + compiler licensing for national inference grids | mature-node manufacturable; standard export-control compliance; licensing revenue on others' capex |
We price just under the market, never near the floor. The floor is the moat, not the price. Every dollar between our floor and the market price is margin nobody else can follow us down to.
Where the models come from
- customers bring their own weights; open models are converted by our compiler (ternary today)
- our W1A1 pretraining runs are the science bet, not a frontier-lab product — we are not competing with OpenAI for models
- we own the format layer: the compiler, the kernels, the silicon it lands on
Wedge logic
- edge ships first: smaller die, mature nodes, cheaper tape-out, faster design wins (roadmap →)
- datacenter follows with the proven fabric scaled up
- every stage is gated by the previous one's proof — no leap-of-faith capex
Why wouldn't NVIDIA do this?
Their moat is generality
CUDA sells flexible GPU programming: every precision, graphics, scientific computing, whichever model is frontier this month. That breadth is what customers pay for.
Generality dies at one bit
CUDA schedules multiplies. HBM streams 16-bit weights. At one bit there is nothing to schedule and nothing to stream — the flexibility has nothing left to sell.
They will support ternary
Kernels for it are certain. But the weights still stream from HBM: best case on a GB300 rack is 457 tok/s per stream at 0.06 J/token — 25× slower, 57× more energy than ours.
The segment is beneath them
Hundreds of billions in revenue, chasing $1T on $3M racks at ~75% margin. A cheaper, simpler $5.5k part is not a market they reorganise for — the innovator's dilemma, on schedule.
Their ceiling assumes perfect 2-bit packed kernels on GB300-class HBM — the best case for them.
Cerebras: same physics, opposite lever.
Cerebras made our diagnosis first: weights must live in SRAM, or you die on the haul. Their fix is to grow the chip 57× — one un-diced wafer. Ours is to shrink the model 16× — one bit. Hover the parts.
STITCHED IN THE SCRIBE LINES
·
900K CORES · FP16/FP8 MACLitho exposes one ~858 mm² reticle at a time — Cerebras wires across the scribe lines (plus spare cores and redundant routing for defects) to fuse 84 fields into one 46,225 mm² fabric. 4T transistors — still multiply-accumulate: the op we delete.
21 PB/sThe point of the wafer — SRAM residency. But N5 SRAM is wafer-priced: ~1,000× HBM per resident GB. And it stopped scaling: WSE-2 → WSE-3 grew logic +54%, SRAM 40 → 44 GB (+10%).
SWARMX IO70B at FP16 is 140 GB > 44 GB — weights stream from external memory boxes, or the model shards across ~4 systems. Off-wafer, the haul returns.
INTEGER THRESHOLDSThe multiply is deleted, not accelerated — sign-match gates, popcount trees, 12-bit accumulators. Logic-grade yield on boring, available CMOS.
NO CoWoSNothing to queue for — the supply chain NVIDIA and Cerebras fight over simply isn’t in the design.
Same thesis, opposite lever — and ~1,000× apart on cost per resident GB. Their scaling axis (more wafer) has stalled with SRAM itself; ours (fewer bits) halves yearly. The honest asymmetry, stated: they run every FP16 checkpoint today; we need binary-native models — the dated bet this deck prices. Cerebras is validation, not refutation: they prove customers pay a premium for SRAM-resident latency.
The CPU: educator, not competitor.
bitnet.cpp proved ternary models run on silicon you already own[1] — free marketing for the binary future. Then volume arrives, and the physics bill comes due. Hover the parts.
OoO · BRANCH PREDICTORS
AVX-512 · POPCNTFlexibility, not tokens: most of the silicon exists to run anything. Binary popcount rides along at a ~0.2 P-op/s ceiling — the batched limit of ~1.5k tok/s per socket.
~0.6 TB/sThe ceiling. Decode re-streams all 8.75 GB of a 70B binary model per token → ~65 tok/s single-stream. At one bit the DRAM haul is 16× lighter — but never deleted.
INTEGER THRESHOLDSFixed-function: every transistor either holds a weight or counts sign-matches. Nothing rides along.
IN PATHThe haul isn’t lighter here — it’s gone.
Same power, three orders of magnitude apart on delivered tokens — because the CPU’s bandwidth ceiling is the DRAM haul, and ours doesn’t exist. The framing for the room: at 16 bits models needed GPUs; at 1 bit they merely run on CPUs — and belong on silicon where the weights never move. CPUs could run graphics in 1995, too. GPUs happened anyway.
Slide the node. See what it builds.
Every number below is a physics ceiling — SRAM density × stacked area, nothing else. Constant at every stop: no CoWoS, no HBM, no N3/N2 allocation — and no kernel NVIDIA can write moves any of it, because their weights still stream from off-package memory at fixed bandwidth. Models are trainable to any of these sizes.
Assumptions
- capacity = SRAM weight budget ÷ bits per weight; single-stream = bandwidth ÷ weight-bytes; batched = × concurrent streams (KV-limited on small stacks)
- max model quoted at trivial KV (batch-1 / short context, KV <1% of weights); dense serving (96 streams × 2k ctx) draws ~25–35% of weight bytes from the same pool — resident model shrinks accordingly
- beyond one package — taller stacks, multi-package, 1T-class: the capacity ladder →
- the ~100 TB/s hybrid-bond port is treated as node-independent — bond pitch is packaging, not lithography; unverified below 7nm-class
- figures marked ~ are engineering estimates; the rest anchor to the chip spec and roadmap NRE classes; ternary capacities (97B · 50B · 15B) carried in the data
The edge line rides the same ladder
- N5 → Invariant-E: 8B on 1 GB on-die, 500 tok/s at 3 W
- 28nm monolithic → E Value: ~1–2B per die, 250 tok/s, ~$34 BOM
- 22–28nm → SE: sub-1B always-on at 0.3 W, ~$14 BOM
The capacity ladder — resident models beyond 70B
| Configuration | Capacity | Max binary model | BOM (est.) | $ / B params |
|---|---|---|---|---|
| 9-die N5 stack — the shipping design | 18 GB | ~144B | ~$7k | ~$50 |
| 16-die tall stack — SoIC roadmaps run 8–12+ high; same bonding flow | 32 GB | ~250B | ~$9–10k | ~$40 |
| 2 packages, 2.5D stitch — only 1–2-bit activations cross | 64 GB | ~500B | ~$18–20k | ~$38 |
| 4 packages, one board | 128 GB | ~1T | ~$36–40k | ~$38 |
| Gain-cell / oxide-semiconductor memory — 2–4× SRAM density; ~2028–30 | 60–120 GB | 0.5–1T | ~$8–12k | ~$10–20 |
| CFET-era SRAM — stacked transistors resume cell scaling; 2030+ | ~50–60 GB | ~450B | ~$12–15k | ~$30 |
| Wafer-scale at N5 density — binary-native, speculative | ~115 GB | ~900B | ~$50–100k system | ~$60–110 |
Capacity scale-out is linear in money: a resident 1T-parameter machine is ~$40k of BOM — four of today’s packages and copper, not a new technology.
$/token stays ~flat as packages multiply (bandwidth scales with capacity) — the cost of size and the cost of tokens are independent dials.
Assumptions
- basis: 2 GB per 800 mm² N5 HD die (~$300); bonding, package and test per the cost model; binary weights at trivial KV; ternary sizes = ÷1.6
- the first four rows need no new technology — taller stacks are the V-Cache flow continued; multi-package interconnect is cheap wires because only sign-class activations cross
- bond-pitch scaling (9 → ~3 µm, demonstrated) multiplies bandwidth, not capacity — tok/s upside on every row, independent of this table
- the gain-cell row is the one memory technology that improves $/parameter ~3×; pre-production — the technology worth tracking
- every row keeps weights resident: the no-kernel-fixes-this argument holds at 1T exactly as at 70B, while a streaming architecture’s ceiling grows only with HBM stack height — the queue they are already in
Node-by-node manufacturing picture: slide the node →
Sources index — every number, one link away
Quantisation research
LLM.int8() GPTQ AWQ QuIP# AQLM BitNet (W1A8) BitNet b1.58 BitNet 2B4T BitNet a4.8 BitNet.cpp SmoothQuant QuaRot SpinQuant ParetoQ Kumar — Scaling Laws for PrecisionCompeting approaches
Sebastian et al. — IMC review (Nat. Nanotech 2020) ISAAC — ADC tax (ISCA 2016) Petersen et al. — logic-gate networks IBM NorthPole (digital near-memory)Gradient-free training
EGGROLL — ES at the Hyperscale (pure-integer) ES at Scale — beyond RL fine-tuning EA4LLM — full-parameter ESAccessed July 2026. MLPerf figures labelled verified/unverified as published. Floor-to-floor comparisons throughout; every derate applied to our side.
What the sharp money asks
"W1A1 at parity doesn't exist."
Correct — that's the deck's stated frame, and every headline number re-prices cleanly on ternary, which does exist (open weights, 2B, FP16 parity). Bit-width at parity has halved yearly for 4 years. Our first milestone is our own 8B W1A1 — the experiment that prices the company.
"Why not just CPUs — bitnet.cpp runs ternary on a laptop."
It does — that's our free marketing. A ~$25k server moves ~0.6 TB/s from DRAM: ~65 tok/s single-stream on a 70B binary, ~1.5k batched at a kilowatt. Our package moves weights zero millimetres: 11,400 and 1.05M at the same power — ~400× tokens/W, ~700× $/throughput. CPUs educate the market and serve low-volume private inference; volume forces the ASIC. Chip-to-chip →
"Precision laws say ~8-bit is optimal."
Those laws fit post-hoc/fixed-budget quantisation; native training keeps bending them (BitNet 2B4T, ParetoQ). And even a 2× effective-param tax leaves ≥55× energy and ~25× latency.
"Where does the KV cache live?"
On-package: MLA-latent + 4-bit, ~3.1 GB at batch 96 × 2k context. Long context pages to LPDDR at a disclosed ~2× derate at 32k. It's a budgeted line item with its own power row.
"100 TB/s of SRAM is fantasy."
It's 21 GB/s/mm² areal across 4,800 mm² of bonded SRAM — less than half of what AMD ships in V-Cache today. MI300X pulls 17 TB/s from one 256 MB layer. Throughput mode already needs 96 TB/s, so latency mode adds no new assumption.
"Groq and Cerebras already do SRAM inference."
At FP8/16 — needing ~576 chips or a 23 kW wafer for 70B. They proved the latency market and the economics of not having small weights. Binary is 16× denser: one 1 kW package. They validated the demand; compression changes the answer.
"NVIDIA just adds binary tensor cores."
The honest risk — it has its own card in the Full Stack slide. The win isn't the MAC: it's weights-in-SRAM (deletes the HBM economics they monetise), binary-native frontier weights (they don't have), and a compiler. Clean-sheet redesign + retraining = a window measured in years.
"Your 1.1M baseline is unverified/offline."
Disclosed on-slide — and it favours them. Offline is their best case; deployed serving runs ~18× worse than the floor we grant them. We compare against their press release, not their reality.
"Fab and packaging capacity?"
Replacing a 100 MW site = 635 chips ≈ ~60 N5 wafers + SoIC capacity — noise against GPU volumes. No CoWoS, no HBM allocation. SRAM dies are redundancy-repairable: high yield on a 2020-era node.
"Why hasn't Google or Microsoft done this?"
BitNet is Microsoft Research — as a paper. Shipping it needs clean-sheet silicon + native pretraining + a compiler, against every incumbent's GPU-portability roadmap. Vertically-integrated fabless labs are the historically successful shape for exactly this move.
"You can't even train W1A1 — backprop dies at sign()."
Two paths. Path A: native QAT with straight-through estimators — how ternary reached parity; we extend that toolchain. Path B: skip backprop entirely — evolution strategies (EGGROLL, 2025) train with forward passes only, in pure integer arithmetic, population-averaging away the noise STE fakes, at ~91% of inference throughput. Path B's workload is millions of cheap forward passes — the exact thing our silicon does 46–118× cheaper. If B scales, the training market lands on our chip too. (Honestly: demonstrated at 1.5B-class fine-tuning, not 70B pretraining.)
"Three founders and no silicon veteran?"
Correct, and the plan is shaped around it: FPGA-first retires the physics risk before the first big cheque; physical design runs with an established design-services partner (the standard fabless path); first silicon hires are a lead SoC architect, an SRAM/memory designer and a packaging lead. The team today is the part nobody can hire: the mathematics and the compiler.
"What do you sell before the chip exists?"
The compiler. It already beats GPTQ/AWQ-class heuristics at 3-/2-bit and ships as an optimisation service on customers' existing GPU fleets, priced as a share of measured savings — cash and design-win relationships years before tape-out. Then edge silicon, then datacenter capacity. Full sequencing in the Business Model appendix.
"The frontier is MoE at 1T params — isn't a 70B die irrelevant?"
Scale-out, not scale-up: only 1–2-bit activations ever cross a package boundary, so a multi-chip fabric is cheap wires, not HBM — the 2-die 2.5D stitch is the proven pattern. And MoE helps us: more parameters per FLOP is exactly what cheap on-die capacity rewards; experts partition naturally one-per-die.
"Why not just distill to a small FP16 model?"
Distillation shrinks the parameter count; it does not change the format. A distilled 8B at FP16 still pays 16× the memory physics of the same model binarised. The two compound — distill, then drop the bits — they do not compete. Our floor applies to whatever size the distillers produce.
"Is 70B ternary at parity actually real today?"
No — and the deck says so: parity is proven at 2B (open weights); 70B is the ~2027 point on a four-year trend. What is already fact in ternary mode is the hardware: the format's energy, cost and capacity numbers. The dated claim is model quality at scale, and we ship datacenter capacity only when open evals pass.
"Can you actually sell to sovereigns?"
We are a fabless company on mature and N5-class nodes with standard export-control compliance; sovereign deals are licensed designs manufactured where lawful — a regulated go-to-market lane, not a gray market. The attraction for the buyer is that nothing in our supply chain is on the EUV frontier.
"Software ecosystem?"
Serving is an OpenAI-compatible API; edge is an SDK; training stays PyTorch. Binary is an inference-format problem we own end-to-end — not a CUDA-replacement problem. Nobody rewrote code for FP8 either.
If a question isn't here, we want it — investment@invariant.fyi